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| a 8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter AD9057 FUNCTIONAL BLOCK DIAGRAM VD PWRDN VDD FEATURES 8-Bit, Low Power ADC: 200 mW Typical 120 MHz Analog Bandwidth On-Chip +2.5 V Reference and T/H 1 V p-p Analog Input Range Single +5 V Supply Operation +5 V or +3 V Logic Interface Power-Down Mode: < 10 mW Three Performance Grades (40 MSPS, 60 MSPS, 80 MSPS) APPLICATIONS Digital Communications (QAM Demodulators) RGB & YC/Composite Video Processing Digital Data Storage Read Channels Medical Imaging Digital Instrumentation AD9057 AIN BIAS OUT VREF IN VREF OUT +2.5V T/H 1k ADC 8 D7-D0 GND ENCODE PRODUCT DESCRIPTION The AD9057 is an 8-bit monolithic analog-to-digital converter optimized for low cost, low power, small size, and ease of use. With a 40 MSPS, 60 MSPS or 80 MSPS encode rates capability and full-power analog bandwidth of 120 MHz, the component is ideal for applications requiring excellent dynamic performance. To minimize system cost and power dissipation, the AD9057 includes an internal +2.5 V reference and a track-and-hold circuit. The user must provide only a +5 V power supply and an encode clock. No external reference or driver components are required for many applications. The AD9057's encode input is TTL/CMOS compatible and the 8-bit digital outputs can be operated from +5 V or +3 V supplies. A power-down function may be exercised to bring total consumption to < 10 mW. In power-down mode the digital outputs are driven to a high impedance state. Fabricated on an advanced BiCMOS process, the AD9057 is available in a space saving 20-lead surface mount plastic package (20 SSOP) and is specified over the industrial (-40C to +85C) temperature range. Customers desiring multichannel digitization may consider the AD9059, a dual 8-bit, 60 MSPS monolithic based on the AD9057 ADC core. The AD9059 is available in a 28-lead surface mount plastic package (28 SSOP) and is specified over the industrial temperature range. PIN CONFIGURATION PWRDN 1 VREF OUT 2 VREF IN 3 GND 4 VD 5 20 D0 (LSB) 19 D1 18 D2 AD9057 17 D3 TOP VIEW 16 GND (Not to Scale) BIAS OUT 6 15 VDD AIN 7 VD 8 GND 9 ENCODE 10 14 D4 13 D5 12 D6 11 D7 (MSB) REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997 AD9057-SPECIFICATIONS Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Gain Error1 Gain Tempco1 ANALOG INPUT Input Voltage Range (Centered at +2.5 V) Input Offset Voltage Input Resistance Input Capacitance Input Bias Current Analog Bandwidth BANDGAP REFERENCE Output Voltage Temperature Coefficient SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 10.3 MHz fIN = 76 MHz Effective Number of Bits fIN = 10.3 MHz fIN = 76 MHz Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10.3 MHz fIN = 76 MHz 2nd Harmonic Distortion fIN = 10.3 MHz fIN = 76 MHz 3rd Harmonic Distortion fIN = 10.3 MHz fIN = 76 MHz Two Tone Intermodulation Distortion (IMD) Differential Phase Differential Gain DIGITAL INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance Encode Pulse Width High (tEH) Encode Pulse Width Low (tEL) 3 (VD = +5 V, VDD = +3 V; external reference) AD9057BRS-40 Min Typ Max 8 AD9057BRS-60 Min Typ Max 8 1.9 2.0 0.75 1.9 2.0 GUARANTEED -6 -2.5 +6 -8 +8 70 0.75 AD9057BRS-80 Min Typ Max 8 1.9 2.0 0.75 1.9 2.0 GUARANTEED -6 -2.5 +6 -8 +8 70 0.75 Units Bits LSB LSB LSB LSB % FS % FS ppm/C Temp Test Level +25C Full +25C Full Full +25C Full Full I VI I VI VI I VI V 1.9 2.0 0.75 1.9 2.0 GUARANTEED -6 -2.5 +6 -8 +8 70 0.75 +25C +25C Full +25C +25C +25C Full +25C Full Full Full Full +25C +25C Full Full +25C +25C V I VI V V I VI V VI V VI IV V V IV IV V V -15 -25 1.0 0 150 2 6 120 +15 +25 -15 -25 1.0 0 150 2 6 120 +15 +25 -15 -25 1.0 0 150 2 6 120 +15 +25 16 25 16 25 16 25 V p-p mV mV k pF A A MHz V ppm/C MSPS MSPS ns ps, rms ns ns ns ns 2.4 2.5 10 2.6 2.4 2.5 10 2.6 2.4 2.5 10 2.6 40 5 2.7 5 6.6 11.5 9 9 60 5 2.7 5 6.6 9.5 9 9 80 5 2.7 5 6.6 8.0 9 9 4.0 4.0 18.0 4.0 14.2 11.3 +25C +25C +25C +25C I V I V 42 45.5 44.0 7.2 7.0 42 45 43.5 7.2 6.9 41.5 45 43.5 7.2 6.9 dB dB Bits Bits 6.7 6.7 6.6 +25C +25C +25C +25C +25C +25C +25C +25C +25C Full Full Full Full +25C +25C +25C I V I V I V V V V VI VI VI VI V IV IV 43 46.5 45.5 -62 -54 -60 -54 -52 0.8 1.0 43 46 45 -62 -54 -60 -54 -52 0.8 1.0 42.5 46 45 -62 -54 -60 -54 -52 0.8 1.0 dB dB dBc dBc dBc dBc dBc Degrees % V V A A pF ns ns -50 -50 -50 -46 -46 -46 2.0 0.8 1 1 4.5 9.0 9.0 166 166 2.0 0.8 1 1 4.5 6.7 6.7 166 166 2.0 0.8 1 1 4.5 5.5 5.5 166 166 -2- REV. B AD9057 Parameter Temp Test Level AD9057BRS-40 Min Typ Max AD9057BRS-60 Min Typ Max AD9057BRS-80 Min Typ Max Units DIGITAL OUTPUTS Logic "1" Voltage (VDD = +3 V) Logic "1" Voltage (VDD = +5 V) Logic "0" Voltage Offset Binary Code POWER SUPPLY VD Supply Current (VD = +5 V) VDD Supply Current (VDD = +3 V)4 Power Dissipation5, 6 Power-Down Dissipation Power Supply Rejection Ratio (PSRR) Full Full Full VI IV VI 2.95 4.95 0.05 V V V Output Coding Full Full Full Full VI VI VI VI 36 4.0 192 6 48 6.5 260 10 15 38 5.5 205 6 48 6.5 260 10 15 40 7.4 220 6 51 8.8 281 10 15 mA mA mW mW mV/V +25C I NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference). 2 tV and t PD are measured from the 1.5 V level of the ENCODE to the 10%/90% levels of the digital output swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of 40 A. 3 SNR/harmonics based on an analog input voltage of -0.5 dBFS referenced to a 1.0 V full-scale input range. 4 Digital supply current based on V DD = +3 V output drive with <10 pF loading under dynamic test conditions. 5 Power dissipation is based on specified encode and 10.3 MHz analog input dynamic test conditions (V D = +5 V 5%, VDD = +3 V 5%). 6 Typical thermal impedance for the RS style (SSOP) 20-pin package: JC = 46C/W, CA = 80C/W, JA = 126C/W. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS Test Level I II III IV V VI Description 100% Production Tested 100% Production Tested at +25C and Sample Tested at Specified Temperatures Sample Tested Only Parameter is Guaranteed by Design and Characterization Testing Parameter is a Typical Value Only 100% Production Tested at +25C; Guaranteed by Design and Characterization Testing for Industrial Temperature Range N AIN N+1 N+2 N+3 N+5 N+4 tA ENCODE tEH tEL tV DIGITAL OUTPUTS N-3 N-2 N-1 N N+1 N+2 tPD MIN tA tEH tEL tV tPD APERTURE DELAY PULSE WIDTH HIGH PULSE WIDTH LOW OUTPUT VALID TIME OUTPUT PROP DELAY 4.0 ns TYP 2.7 ns MAX 166 ns 166 ns 6.6 ns 9.5 ns Figure 1. Timing Diagram REV. B -3- AD9057 ABSOLUTE MAXIMUM RATINGS PIN DESCRIPTIONS Pin No. 1 Name PWRDN Function Power-Down Function Select; Logic HIGH for Power-Down Mode (Digital Outputs Go to High Impedance State). Internal Reference Output (+2.5 V typ); Bypass with 0.1 F to Ground. Reference Input for ADC (+2.5 V typ, 10%). Ground (Analog/Digital). Analog +5 V Power Supply. Bias Pin for AC Coupling (1 k to REF IN). Analog Input for ADC. Encode Clock for ADC (ADC Samples on Rising Edge of ENCODE). Digital Outputs of ADC. Digital Output Power Supply. Nominally +3 V to +5 V. VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V Analog Inputs . . . . . . . . . . . . . . . . . . . . -0.5 V to VD + 0.5 V Digital Inputs . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V VREF Input . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VD + 0.5 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . +175C Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150C ORDERING GUIDE 2 VREF OUT 3 4, 9, 16 5, 8 6 7 10 VREF IN GND VD BIAS OUT AIN ENCODE Model Temperature Range Package Option* AD9057BRS-40, -60, -80 -40C to +85C RS-20 AD9057/PCB +25C Evaluation Board *RS = Shrink Small Outline (SSOP). Table I. Digital Coding (VREF = +2.5 V) Analog Input 3.0 V 2.502 V 2.498 V 2.0 Voltage Level Positive Full Scale Midscale +1/2 LSB Midscale -1/2 LSB Negative Full Scale Digital Output 1111 1111 1000 0000 0111 1111 0000 0000 11-14, 17-20 15 D7-D4, D3-D0 VDD PIN CONFIGURATION PWRDN 1 VREF OUT 2 VREF IN 3 GND 4 VD 5 20 D0 (LSB) 19 D1 18 D2 AD9057 17 D3 TOP VIEW 16 GND (Not to Scale) BIAS OUT 6 15 VDD AIN 7 VD 8 GND 9 ENCODE 10 14 D4 13 D5 12 D6 11 D7 (MSB) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9057 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE -4- REV. B Typical Performance Characteristics-AD9057 0 -10 -20 -30 ENCODE = 60MSPS ANALOG IN = 10.3MHz, -0.5dBFS SINAD = 46.1dB ENOB = 7.36 BITS SNR = 46.5dB -30 -35 -40 -45 ENCODE = 60MSPS AIN = -0.5dBFS -40 dB 2ND HARMONIC dB -50 -55 -50 -60 -70 -80 -90 3RD HARMONIC -60 -65 -70 0 20 40 60 80 100 120 140 160 ANALOG INPUT FREQUENCY - MHz 0 FREQUENCY - MHz 30 Figure 2. Spectral Plot 60 MSPS, 10.3 MHz Figure 5. Harmonic Distortion vs. AIN Frequency 0 ENCODE = 60MSPS -10 ANALOG IN = 76MHz, -0.5dBFS SINAD = 44.9dB ENOB = 7.16 BITS -20 SNR = 45.2dB -30 -40 dB 0 -10 -20 -30 -40 dB ENCODE = 60MSPS F1 IN = 9.5MHz @ -7.0dBFS F2 IN = 9.9MHz @ -7.0dBFS 2F1 - F2 = -52.0dBc 2F2 - F1 = -53.0dBc -50 -60 -70 -80 -90 -50 -60 -70 -80 -90 0 FREQUENCY - MHz 30 0 10 20 FREQUENCY - MHz 30 Figure 3. Spectral Plot 60 MSPS, 76 MHz Figure 6. Two-Tone Intermodulation Distortion 48 46 44 42 40 SINAD dB 54 SNR 48 42 SNR SINAD 36 30 AIN = 10.3MHz, -0.5dBFS 24 dB 38 36 ENCODE = 60MSPS AIN = -0.5dBFS 18 34 32 30 0 12 0 20 40 60 80 100 120 ANALOG INPUT FREQUENCY - MHz 140 160 5 10 20 30 40 50 60 ENCODE RATE - MSPS 70 80 90 Figure 4. SINAD/SNR vs. AIN Frequency Figure 7. SINAD/SNR vs. Encode Rate REV. B -5- AD9057-Typical Performance Characteristics 350 300 VDD = +5V 250 12 11 10 9.5 9.0 VDD = +3V tPD - ns 200 mW VDD = +3V 150 100 AIN = 10.3MHz, -0.5dBFS 50 8.5 8.0 7.5 7.0 6.5 VDD = +5V 0 5 10 20 30 40 50 60 ENCODE RATE - MSPS 70 80 90 6.0 -45 0 25 TEMPERATURE - C 70 90 Figure 8. Power Dissipation vs. Encode Rate Figure 11. tPD vs. Temperature/Supply (VDD = +3 V/+5 V) 46.5 46.0 45.5 45.0 44.5 SINAD SNR 46.5 46 SNR 45.5 45 dB dB ENCODE = 60MSPS AIN = 10.3MHz, -0.5dBFS 44.0 43.5 43.0 42.5 42.0 41.5 -45 0 25 TEMPERATURE - C 70 90 44.5 44 SINAD 43.5 43 42.5 5.8 ENCODE = 60MSPS AIN = 10.3MHz, -05dBFS 6.7 8.35 9.2 7.5 10 ENCODE HIGH PULSE WIDTH - ns 10.9 Figure 9. SINAD/SNR vs. Temperature Figure 12. SINAD/SNR vs. Encode Pulse Width 0 -1 -2 0 -0.2 -0.4 -3 GAIN ERROR - % ADC GAIN - dB -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -45 -4 -5 -6 -7 -8 -9 -10 1 2 ENCODE = 60MSPS AIN = -0.5dBFS 0 25 TEMPERATURE - C 70 90 5 10 20 50 100 ANALOG FREQUENCY - MHz 200 500 Figure 10. ADC Gain vs. Temperature (with External +2.5 V Reference) Figure 13. ADC Frequency Response -6- REV. B AD9057 THEORY OF OPERATION +5V The AD9057 combines Analog Devices' proprietary MagAmp gray code conversion circuitry with flash converter technology to provide a high performance, low cost ADC. The design architecture ensures low power, high speed, and 8-bit accuracy. A single-ended TTL/CMOS compatible ENCODE input controls ADC timing for sampling the analog input pin and strobing the digital outputs (D7-D0). An internal voltage reference (VREF OUT) may be used to control ADC gain and offset or an external reference may be applied. The analog input signal is buffered at the input of the ADC and applied to a high speed track-and-hold. The T/H circuit holds the analog input value during the conversion process (beginning with the rising edge of the ENCODE command). The T/H's output signal passes through the gray code and flash conversion stages to generate coarse and fine digital representations of the held analog input level. Decode logic combines the multistage data and aligns the 8-bit word for strobed outputs on the rising edge of the ENCODE command. The MagAmp/Flash architecture of the AD9057 results in three pipeline delays for the output data. USING THE AD9057 Analog Inputs 2 REF OUT 10k 10k +5V AD8041 1k VIN (-0.5V TO +0.5V) 1k 7 AIN 0.1F AD9057 3 REF IN Figure 15. DC Coupled AD9057 (Inverted VIN) Voltage Reference A stable and accurate +2.5 V voltage reference is built into the AD9057 (VREF OUT). The reference output may be used to set the ADC gain/offset by connecting VREF OUT to VREF IN. The internal reference is capable of providing 300 A of drive current (for dc biasing the analog input or other user circuitry). Some applications may require greater accuracy, improved temperature performance, or gain adjustments which cannot be obtained using the internal reference. An external voltage may be applied to the VREF IN with VREF OUT disconnected for gain adjustment of up to 10% (the VREF IN pin is internally tied directly to the ADC circuitry). ADC gain and offset will vary simultaneously with external reference adjustment with a 1:1 ratio (a 2% or 50 mV adjustment to the +2.5 V reference varies ADC gain by 2% and ADC input range center offset by 50 mV). Theoretical input voltage range versus reference input voltage may be calculated from the following equations: VRANGE (p-p) VMIDSCALE VTOP-OF-RANGE = VREF IN/2.5 = VREF IN = VREF IN + VRANGE/2 The AD9057 provides a single-ended analog input impedance of 150 k. The input requires a dc bias current of 6 A (typical) centered near +2.5 V ( 10%). The dc bias may be provided by the user or may be derived from the ADC's internal voltage reference. Figure 14 shows a low cost dc bias implementation allowing the user to capacitively couple ac signals directly into the ADC without additional active circuitry. For best dynamic performance, the VREF OUT pin should be decoupled to ground with a 0.1 F capacitor (to minimize modulation of the reference voltage) and the bias resistor should be approximately 1 k. A 1 k bias resistor ( 20%) is included within the AD9057 and may be used to reduce application board size and complexity. +5V VBOTTOM-OF-RANGE = VREF IN - VRANGE/2 Digital Logic (+5 V/+3 V Systems) 2 REF OUT REF IN 1k 6 0.1F VIN (1V p-p) 7 AIN BIAS OUT 0.1F 3 The digital inputs and outputs of the AD9057 can easily be configured to interface directly with +3 V or +5 V logic systems. The ENCODE and power-down (PWRDN) inputs are CMOS stages with TTL thresholds of 1.5 V, making the inputs compatible with TTL, +5 V CMOS, and +3 V CMOS logic families. As with all high speed data converters, the encode signal should be clean and jitter free to prevent degradation of ADC dynamic performance. The AD9057's digital outputs will also interface directly with +5 V or +3 V CMOS logic systems. The voltage supply pin (VDD) for these CMOS stages is isolated from the analog VD voltage supply. By varying the voltage on this supply pin the digital output HIGH level will change for +5 V or +3 V systems. Optimum SNR is obtained running the outputs at +3 V. Care should be taken to isolate the VDD supply voltage from the +5 V analog supply to minimize digital noise coupling into the ADC. AD9057 Figure 14. Capacitively Coupled AD9057 Figure 15 shows typical connections for high performance dc biasing using the ADC's internal voltage reference. All components may be powered from a single +5 V supply (in the example analog input signals are referenced to ground). REV. B -7- AD9057 The AD9057 provides high impedance digital output operation when the ADC is driven into power-down mode (PWRDN, logic HIGH). A 200 ns (minimum) power-down time should be provided before a high impedance characteristic is required at the outputs. A 200 ns power-up period should be provided to ensure accurate ADC output data after reactivation (valid output data is available three clock cycles after the 200 ns delay). Timing full-power analog bandwidth of 2x the maximum sampling rate, the ADC provides sufficient pixel to pixel transient settling time to ensure accurate 60 MSPS video digitization. Figure 17 shows a typical RGB video digitizer implementation for the AD9057. 8 RED AD9057 The AD9057 is guaranteed to operate with conversion rates from 5 MSPS to 80 MSPS depending on grade. The ADC is designed to operate with an encode duty cycle of 50%, but performance is insensitive to moderate variations. Pulse width variations of up to 10% (allowing the encode signal to meet the minimum/maximum HIGH/LOW specifications) will cause no degradation in ADC performance (see Figure 1 timing diagram). Power Dissipation 8 GREEN AD9057 8 BLUE AD9057 PIXEL CLOCK H-SYNC PLL The power dissipation of the AD9057 is specified to reflect a typical application setup under the following conditions: analog input is -0.5 dBFS at 10.3 MHz, VD is +5 V, VDD is +3 V, and digital outputs are loaded with 7 pF typical (10 pF maximum). The actual dissipation will vary as these conditions are modified in user applications. Figure 8 shows typical power consumption for the AD9057 versus ADC encode frequency and VDD supply voltage. A power-down function allows users to reduce power dissipation when ADC data is not required. A TTL/CMOS HIGH signal (PWRDN) shuts down portions of the ADC and brings total power dissipation to less than 10 mW. The internal bandgap voltage reference remains active during power-down mode to minimize ADC reactivation time. If the power-down function is not desired, Pin 1 should be tied to ground. APPLICATIONS Figure 17. RGB Video Encoder Evaluation Board The AD9057/PCB evaluation board provides an easy to use analog/digital interface for the 8-bit, 60 MSPS ADC. The board includes typical hardware configurations for a variety of high speed digitization evaluations. On board components include the AD9057 (in the 20-pin SSOP package), an optional analog input buffer amplifier, a digital output latch, board timing drivers, an analog reconstruction digital-to-analog converter, and configurable jumpers for ac coupling, dc coupling, and power-down function testing. The board is configured at shipment for dc coupling using the AD9057's internal voltage reference. For dc coupled analog input applications, amplifier U2 is configured to operate as a unity gain inverter with adjustable offset for the analog input signal. For full-scale ADC drive the analog input signal should be 1 V p-p into 50 (R1) referenced to ground (0 V). The amplifier offsets the analog signal by +VREF (+2.5 V typical) to center the voltage for proper ADC input drive. For dc coupled operation, connect E1 to E2 (analog input to R2) and E11 to E12 (amplifier output to analog input of AD9057) using the board jumper connectors. DC offset of the analog input signal can be modified by adjusting potentiometer R10. For ac coupled analog input applications, amplifier U2 is removed from the analog signal path. The analog signal is coupled into the input of the AD9057 through capacitor C2. The ADC pulls analog input bias current from the VREF IN voltage through the 1 k resistor internal to the AD9057 (BIAS OUT). The analog input signal to the board should be 1 V p-p into 50 (R1) for full-scale ADC drive. For ac coupled operation, connect E1 to E3 (analog input A to C2 feedthrough capacitor) and E10 to E12 (C2 to the analog input and internal bias resistor) using the board jumper connectors. The onboard reference voltage may be used to drive the ADC or an external reference may be applied. To use the internal voltage reference, connect E6 to E5 (VREF OUT to VREF IN). To apply an external voltage reference, connect E4 to E5 (external reference from the REF banana jack to VREF IN). The external voltage reference should be +2.5 V 10%. The wide analog bandwidth of the AD9057 makes it attractive for a variety of high performance receiver and encoder applications. Figure 16 shows two ADCs in a typical low cost I & Q demodulator implementation for cable, satellite, or wireless LAN modem receivers. The excellent dynamic performance of the ADC at higher analog input frequencies and encode rates empowers users to employ direct IF sampling techniques (refer to Figure 3 spectral plot). IF sampling eliminates or simplifies analog mixer and filter stages to reduce total system cost and power. BPF IF IN 90 BPF AD9057 AD9057 VCO VCO Figure 16. I & Q Digital Receiver The high sampling rate and analog bandwidth of the AD9057 are ideal for computer RGB video digitizer applications. With a -8- REV. B AD9057 The power-down function of the AD9057 can be exercised through a board jumper connection. Connect E7 to E9 (+5 V to PWRDN) for power-down operation. For normal operation, connect E8 to E9 (ground to PWRDN). The encode signal source should be TTL/CMOS compatible and capable of driving a 50 termination (R7). The digital outputs of the AD9057 are buffered through latches on the evaluation board (U3) and are available for the user at connector Pins 30-37. Latch timing is derived from the ADC ENCODE clock and a digital clocking signal is provided for the board user at connector Pins 2 and 21. An onboard reconstruction digital-to-analog converter is available for quick evaluations of ADC performance using an oscilloscope or spectrum analyzer. The DAC converts the ADC's digital outputs to an analog signal for examination at the DAC OUT connector. The DAC is clocked at the ADC ENCODE frequency. The AD9760 is a 10-bit/100 MSPS single +5 V supply DAC. The reconstruction signal facilitates quick system troubleshooting or confirmation of ADC functionality without requiring external digital memory, timing, or display interfaces. The DAC can be used for limited dynamic testing, but customers should note that test results will be based on the combined performance of the ADC and DAC (the best ADC performance will be recognized by evaluating the digital outputs of the ADC directly). +VD +VD ENCODE AIN PWRDN 500 VREFIN Digital Inputs Analog Input +VDD, +3V TO +5V +VD 1k D0-D7 VREFIN BIAS OUT Digital Outputs Bias Output +VD +VD 3k VREFOUT VREFIN 2.5k VREF Output VREF Input Figure 18. Equivalent Circuits REV. B -9- AD9057 E7 +5V J6, REF C17 0.1F E4 8 7 6 5 E5 R5 2k R10 500 R4 2k R6 10 E11 E12 E10 +5V GND E6 C1 0.1F PWRDN (LSB) D0 REF OUT D1 REF IN D2 GND D3 VD GND 6 BIAS OUT VDD 7 AIN D4 8 VD D5 9 GND D6 10 ENC (MSB) D7 1 2 3 4 5 20 19 18 17 16 15 14 13 12 11 D0 D1 D2 D3 GND VDD D4 D5 D6 D7 U3 74ACQ574 D7 D6 D5 D4 D3 D2 D1 D0 9 8 7 6 5 4 3 2 8D 7D 6D 5D 4D 3D 2D 1D CK 11 C2 0.1F 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q OE 1 12 13 14 15 16 DA7 DA6 DA5 DA4 DA3 17 DA2 18 DA1 19 DA0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 3 U4 74AC00 4 5 U4 74AC00 12 13 U4 74AC00 9 10 8 11 6 28 DAC AD9760AR +5V 27 24 23 19 18 17 16 15 C13 0.1F R9 2k +5V +5V C18 0.1F 22 23 24 25 26 27 28 29 DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 30 31 32 33 34 35 36 37 E9 E8 PWRDN GND ANALOG IN R2 E2 1k E1 E3 R1 50 U2 AD8041Q 1 NC 2 3 4 -VS R3 1k DIS +VS NC C37DRPF P2 BNC J1 GND +5V BNC J3 ENCODE R7 50 U4 74AC00 1 2 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 GND GND 1 2 3 4 5 6 7 8 9 10 CLK DVDD (MSB) DB9 AVDD DB8 COMP2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) COMP1 FSADJ REFIO REFLO SLEEP C19 0.1F J7, VDD VDD C10 + 0.1F C11 10F ANALOG RECONSTRUCT DAC OUT BNC J2 IOUT A B 22 21 PWRDN R8 50 R11 50 J4, GND C7 0.1F J5, +5V C3 0.1F DECOUPLING CAPS C4 0.1F C5 0.1F + C9 0.1F C12 10F C8 0.1F C14 0.1F Figure 19. Evaluation Board Schematic -10- REV. B AD9057 Figure 20. Evaluation Board Layout REV. B -11- AD9057 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead SSOP (RS-20) 0.295 (7.50) 0.271 (6.90) 20 11 0.311 (7.9) 0.301 (7.64) 1 10 0.078 (1.98) PIN 1 0.068 (1.73) 0.07 (1.78) 0.066 (1.67) 0.212 (5.38) 0.205 (5.21) 0.008 (0.203) 0.002 (0.050) 0.0256 (0.65) BSC SEATING 0.009 (0.229) PLANE 0.005 (0.127) 8 0 0.037 (0.94) 0.022 (0.559) -12- REV. B PRINTED IN U.S.A. C2156b-2-4/97 |
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